1. Field
Apparatuses and methods consistent with the present disclosure relate to a device having a secure debugging circuit and a debugging method of the same.
2. Description of Related Art
In recent years, malicious users have increased attacks on products that include Application Processors (APs). These malicious users have used an attach technique to gain malicious access to an AP. Thus, in response, a secure level of the AP product has been reinforced. In particular, there is research on a secure debugging circuit (hereinafter, referred to as “Secure JTAG”) provided through a Joint Test Action Group (JTAG) port, because the JTAG port provides high controllability and observability on an AP chip. Secure JTAG authentication is divided into password authentication and challenge-response authentication.
The password authentication is prone to a replay attack, and it is easily exposed to a dictionary attack if the complexity of the password is low. Also, since a user knows the password, it is difficult to prevent a password from being exposed to a malicious user. In case of the password authentication, it is difficult to provide multiple, different access controls. Moreover, in many cases, different passwords are assigned to access controls, respectively. Therefore, even though the number of passwords may be reduced through a hierarchical structure, a plurality of passwords are required. In the case of a plurality of passwords, password management is difficult, and comparison with each password is required at authentication. Thus, a time for authentication may increase with the increase in the number of passwords.
In case of the challenge-response authentication, a request for executing an authentication protocol is simply to set an open signal. This may mean that the authentication protocol can be executed by any aggressor.